`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    01:55:23 05/02/2013 
// Design Name: 
// Module Name:    CPU 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CPU(
    input inst_ex,
    input [7:0] inst_data,
	 input reset_b,
    input clk_50Mhz,
    input reg_read,
    output [15:0] reg_data
    );
	 wire [7:0] result;
	 wire [3:0] data_to_reg, regA, regB;
	 wire [1:0] addr_to_reg;
	 wire LDR, sum, cmp, mul, r_pulse;

	Decoder decoder1 (.clk_50Mhz(clk_50Mhz), .reset_b(reset_b), .pop_data(inst_ex), .data_i(inst_data), .data_o(data_to_reg), .addr(addr_to_reg), .LDR(LDR), .sum(sum), .cmp(cmp), .mul(mul));
	reg_set regset1(.clk_50Mhz(clk_50Mhz), .reset_b(reset_b), .result(result), .regA(regA), .regB(regB), .read(reg_read), .addr_i(addr_to_reg), .data_i(data_to_reg), .data_o(reg_data), .LDR(LDR), .result_pulse(r_pulse));
	ALU alu1 (.clk_50Mhz(clk_50Mhz), .reset_b(reset_b), .sum(sum), .cmp(cmp), .mul(mul), .regA(regA), .regB(regB), .result(result), .o_pulse(r_pulse));

endmodule


